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XE1201A Data Sheet
TLA RFA RFB DEMODULATOR SYMBOL SYN CHRO TLB FILTERING + IO OFFSET REDUCTION QO AVDD AGND DVDD DGND
RXD
CLKD
SD BUS CONTROL POWER MANAGEMENT 90 DEG SC DE
EN RF POWER AMP RFOU T DDS TXD RXTX
VREF
90 DEG
LO CLOCK
TPA
TPB
RFGN D
RFVDD
TKA
TKB
TKC
SWA
SWB
LOGND
XTAL
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Cool Solutions
XEMICS SA, Switzerland Tel: +41 32 720 51 70 Fax: +41 32 720 57 70 e-mail: info@xemics.com Web:www.xemics.com
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RFOUT RFA TLA RFVDD
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NAME EN DE AVDD TPA TPB AGND SC SD LOGND TKA TKB TKC SWA SWB RXTX VREF TXD CLKD RXD DGND XTAL XTAL DVDD QO IO RFA RFB RFGND RFOUT TLA TLB RFVDD
DESCRIPTION
EN
RFGND
RFB
TLB
IO QO DVDD XTAL XTAL DGND RXD CLKD TXD VREF
Chip enable Bus data enable Supply voltage for analog Power amplifier tank circuit Power amplifier tank circuit Ground for analog Bus clock Bus data input Ground for local oscillator Oscillator tank circuit Oscillator tank circuit Oscillator tank circuit SAW resonator SAW resonator Receiver / transmitter enable Voltage stabilizer decoupling Data input stream Received data clock Received data output Ground for digital Reference oscillator Reference oscillator Supply voltage for digital Test pin Test pin RF input RF input Ground for RF Transmitter output Low noise amplifier tank circuit Low noise amplifier tank circuit Supply voltage for RF
DE AVDD TPA TPB AGND SC LOGND SD RXTX
SWA
fig. 2: TQFP 32L package
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Tamb = 25 C; VDD = 3.0 V; FLO = 433.92 MHz; +/- 125 kHz frequency deviation; 16 kbit/s pseudo random bit sequence unless otherwise specified
SWB
TKA
TKC
TKB
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SYMBOL PARAMETER VDD IDDR IDDT Operating supply voltage Reception supply current Transmission supply current
CONDITIONS
Min 2.4 4.5
Typ 3.0 6 5.5 8 11 13.5
Max Units 5.5 7.5 V mA mA mA mA mA 65 1 500
- 15 dBm output power - 5 dBm output power + 2.5 dBm output power + 5 dBm output power Clock running Clock stopped 300 C13 = 0 ; C12 = 0 C13 = 0 ; C12 = 1 C13 = 1 ; C12 = 0 C13 = 1 ; C12 = 1 BER=1%, Rsource = 50 8 kbit/s 16 kbit/s 64 kbit/s Parallel real part Parallel capacitive part Parallel capacitive part Funw =FLO 125 kHz RFlevel = RFS+3dB Funw =FRF 1MHz RFlevel = RFS+3dB 1 channel, BER=1% 3 dB cutoff frequency -40 < Tamb < +85 C 2.4 V < Vdd < 3.6 V -106 -104 -99 -12 39 0 250 programmable by 3-wire bus programmable by 3-wire bus +/-4 4 0
IDDS FR TP
Standby current Frequency range Transmitter output power
55 0.2 -15 -5 +2 +5 -109 -107 -102 1 4 2.4 -7 43 330 -4 +/-8 160 -
A A
MHz dBm dBm dBm dBm
RFS
RF sensitivity
410 +/-15 -
dBm dBm dBm k pF pF dB dB dBm kHz ppm/
C
ZIN ZOUT CCR BI ML BW LOD LOS TBW FDEV DR LOL
RF input impedance RF output impedance Co-channel rejection Blocking immunity Maximum receiver input level Baseband filter bandwidth Local oscillator drift Local oscillator shift DDS anti-alias filter bandwidth Frequency deviation Data rate Digital input/output low level
KHz kHz
+/-200 kHz 64 0.4 kbit/s V
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SYMBOL PARAMETER HIL Tclk Rwu Twu Tsu Trt Ttr Tr Tf FSC Digital input/output high level Clock wake-up time Receiver wake-up time Transmitter wake-up time Data set-up time Receive to transmit switching time Transmit to receive switching time SC bus clock rise time SC bus clock fall time SC bus clock frequency
CONDITIONS
Min 2.6
Typ 2 60 60 15 60 -
Max Units 3 3.5 75 75 25 75 50 50 4 V ms
from cold start (see fig. 5) from oscillator running (see fig. 4) bit synchronizer bypassed from oscillator running (see fig. 4) (see fig. 3) (see fig. 4) (see fig. 4) bit synchronizer bypassed
125 -
s s
ns
s s
ns ns MHz
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3-wire Bus Data Format
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Tsu Tsu
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SC
SD
D15 MSB
D14
A,B,C13
A,B,C12
A,B,C1
A,B,C0 LSB
Figure 3: timing diagram for 3-wire bus
Rwu
ready to receive
Ttr
ready to transmit
EN
RXTX
RECEIVE MODE
TRANSMIT MODE
Figure 4: timing diagram for RXTX and EN control pins
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ready to transmit or receive EN Tclk Twu
Figure 5: timing diagram for chip wake-up (from cold start)
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SY9AvA (
measurement conditions: 16 kbit/s - RFlevel = -102 dBm
Figure 6: Received data stream with internal bit synchronizer bypassed
SY9AvA (
8GF9AvA '
measurement conditions: 16 kbit/s - RFlevel = -102 dBm
Figure 7: Received data stream with internal bit synchronizer and synchronised data clock output
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components side (front)
copper side (back)
Figure 8: reference board layout (not actual scale)
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$QDORJ 3LQ 'HVFULSWLRQ
Vdd 1k2 1k2 pi n12
p i n4
Vdd 1k3 1k3
pi n10
p i n5
pin13
pi n1 4
p i n1 1
p in 4 a n d 5 : p o w e r a m p lif ie r
p in 1 0 , 1 1 , 1 2 , 1 3 a n d 1 4 : o s c illa t o r
pin21
2p2
pin22
3p
5p
p i n1 6
p in 1 6 : vo lt a g e s t a b il iz e r
p in 2 1 a n d 2 2 : c lo c k o s c illa t o r
p i n2 6 p i n24, 25
p i n2 7
p in 2 4 a n d 2 5 : I an d Q o u t p u t s
p in 2 6 a n d 2 7 : R F a m p lif ie r in p u t s
pi n3 0
pi n3 1
pin2 9
p in 2 9 : t r a n s m it t e r o u tp u t
p in 3 0 an d 3 1 : L N A t an k
Figure 9: analog pins description
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VDD 12nH ustrip 2.7 pF VDD 10nF 12nH ustrip
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I O
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AGND
DVDD
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FROM ANTENNA
18nH ustrip 2.2pF
RFB DEMODULATOR SYMBOL SYNCHRO
RXD
CLKD
DATA OU TPUT
2.2pF
S D BUS CONTROL 90 DEG POWER MANAGEMENT S C DE E N
VDD 3.3pF 50 OHM 18nH ustrip
CHIP CONTROL
RF POWER AMP RFOUT
RXTX
2.2pF TO ANTENNA
DDS
TXD
DATA INPUT
VREF
10nF
90 DEG L O CLOCK TPA TPB RFGND RFVDD TKA TKB TKC SWA LOGND XTAL
SWB
2.2pF
VDD
27nH
10nF 12nH 12nH
2 - 6pF 12nH 12nH SAW RESON ATOR RFM R02101A
4 MHz IQD HC43
10nF VDD
Figure 10: application information
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0HFKDQLFDO 'DWD 3DFNDJH
DIMENSIONS Body Thickness Footpint (Body+) A A1 A2 D D1 E E1 L e b ccc ddd 0
VALUE 1.00 2.00 1.20 0.05 min/0.15 max 1.00 9.00 7.00 9.00 7.00 0.60 0.80 0.35 0.10 0.20 0-7
Package Information for TQFP 32L
TOLERANCE MAX 0.05 0.25 0.10 0.25 0.10 +0.15/-0.10 BASIC 0.05 MAX MAX
XEMICS, 2001
All rights reserved. Reproduction of whole or part of this document is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in Switzerland Date of release 02-01
D0101-118

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